{"id":2580,"date":"2021-09-13T12:06:00","date_gmt":"2021-09-13T09:06:00","guid":{"rendered":"http:\/\/selftiming.ru\/new\/?p=2580"},"modified":"2023-04-07T16:51:50","modified_gmt":"2023-04-07T13:51:50","slug":"design-validation-of-recurrent-signal-processor-fpga-prototype","status":"publish","type":"post","link":"http:\/\/selftiming.ru\/new\/2021\/09\/13\/design-validation-of-recurrent-signal-processor-fpga-prototype\/","title":{"rendered":"Design validation of recurrent signal processor FPGA prototype"},"content":{"rendered":"\n

Yury Stepchenkov, Dmitry Khilko, Yury Shikunov and Georgy Orlov. Design validation of recurrent signal processor FPGA prototype \/\/ Proceedings of IEEE East-West Design & Test Symposium (EWDTS\u20192021),  Batumi, Georgia, September, 10 — 13, 2021, P. 157-161.<\/p>\n\n\n\n

DOI: <\/strong>10.1109\/EWDTS52692.2021.9581005. (Indexed in Scopus). URL: https:\/\/ieeexplore.ieee.org\/document\/9581005<\/a>.<\/p>\n\n\n\n

\u0424\u0438\u043d\u0430\u043d\u0441\u043e\u0432\u0430\u044f \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u0430:<\/strong> \u0418\u0441\u0441\u043b\u0435\u0434\u043e\u0432\u0430\u043d\u0438\u0435 \u0432\u044b\u043f\u043e\u043b\u043d\u0435\u043d\u043e \u043f\u0440\u0438 \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u0435 \u0420\u043e\u0441\u0441\u0438\u0439\u0441\u043a\u043e\u0433\u043e \u043d\u0430\u0443\u0447\u043d\u043e\u0433\u043e \u0444\u043e\u043d\u0434\u0430 (\u043f\u0440\u043e\u0435\u043a\u0442 19-11-00334). \/ Funding Agency<\/strong>: The research was supported by the Russian Science Foundation (project No. 19-11-0034).<\/p>\n\n\n\n

Abstract:<\/strong> This paper describes the final stage of the FPGA prototype development of a recurrent signal processor. During the development of this prototype, a set of tools was created, based on which design verification was carried out. We describe the development process and the prototype validation methodology on a class of DSP tasks using a demo task of isolated word recognition. Taking the previously developed tools and methods for verifying software and hardware models, we have developed a specialized design validation tool. This solution made it possible to ensure the uniformity of the validation process for various types of architecture implementation and to establish the correctness of their operation.<\/p>\n\n\n\n

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\u0414\u043e\u043f\u043e\u043b\u043d\u0438\u0442\u0435\u043b\u044c\u043d\u0443\u044e \u0438\u043d\u0444\u043e\u0440\u043c\u0430\u0446\u0438\u044e \u043e \u0441\u043e\u0434\u0435\u0440\u0436\u0430\u043d\u0438\u0438 \u0434\u043e\u043a\u043b\u0430\u0434\u0430 \u0432\u044b \u043c\u043e\u0436\u0435\u0442\u0435 \u043f\u043e\u043b\u0443\u0447\u0438\u0442\u044c \u043d\u0430 \u0441\u0430\u0439\u0442\u0435 \u043a\u043e\u043d\u0444\u0435\u0440\u0435\u043d\u0446\u0438\u0438<\/a> \/ You can get additional information on the content of the article on the conference website<\/a>. \u0422\u0430\u043a\u0436\u0435 \u0432\u044b \u043c\u043e\u0436\u0435\u0442\u0435 \u0441\u0432\u044f\u0437\u0430\u0442\u044c\u0441\u044f \u0441 \u0430\u0432\u0442\u043e\u0440\u0430\u043c\u0438 \u0434\u043e\u043a\u043b\u0430\u0434\u0430, \u0438\u043b\u0438 \u0441 \u0440\u0443\u043a\u043e\u0432\u043e\u0434\u0438\u0442\u0435\u043b\u0435\u043c \u043d\u0430\u0443\u0447\u043d\u043e\u0439 \u0433\u0440\u0443\u043f\u043f\u044b \u0421\u0442\u0435\u043f\u0447\u0435\u043d\u043a\u043e\u0432\u044b\u043c \u042e. \u0410. ia_ste@mail.ru<\/a> \/ You can also contact the authors of the report, or with the head of the scientific group Stepchenkov Ya. A. ia_ste@mail.ru<\/a>
<\/p>\n\n\n\n

Download PRESENTATION<\/a><\/div>\n","protected":false},"excerpt":{"rendered":"

Yury Stepchenkov, Dmitry Khilko, Yury Shikunov and Georgy Orlov. Design validation of recurrent signal processor FPGA prototype \/\/ Proceedings of IEEE East-West Design & Test Symposium (EWDTS\u20192021),  Batumi, Georgia, September, 10 — 13, 2021, P. 157-161. DOI: 10.1109\/EWDTS52692.2021.9581005. (Indexed in Scopus). URL: https:\/\/ieeexplore.ieee.org\/document\/9581005. \u0424\u0438\u043d\u0430\u043d\u0441\u043e\u0432\u0430\u044f \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u0430: \u0418\u0441\u0441\u043b\u0435\u0434\u043e\u0432\u0430\u043d\u0438\u0435 \u0432\u044b\u043f\u043e\u043b\u043d\u0435\u043d\u043e \u043f\u0440\u0438 \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u0435 \u0420\u043e\u0441\u0441\u0438\u0439\u0441\u043a\u043e\u0433\u043e \u043d\u0430\u0443\u0447\u043d\u043e\u0433\u043e \u0444\u043e\u043d\u0434\u0430 (\u043f\u0440\u043e\u0435\u043a\u0442 19-11-00334). \/ […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[28,60,13,53,15,59],"tags":[],"class_list":["post-2580","post","type-post","status-publish","format-standard","hentry","category-28","category-orlov-g-a","category-rekurentnost","category-stepchenkov-yu-a","category-conferences-rekurentnost","category-hilko-d-v"],"yoast_head":"\nDesign validation of recurrent signal processor FPGA prototype - \u041f\u0435\u0440\u0441\u043f\u0435\u043a\u0442\u0438\u0432\u043d\u044b\u0435 \u043f\u0443\u0442\u0438 \u0440\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 \u0430\u043f\u043f\u0430\u0440\u0430\u0442\u0443\u0440\u044b<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/selftiming.ru\/new\/2021\/09\/13\/design-validation-of-recurrent-signal-processor-fpga-prototype\/\" \/>\n<meta property=\"og:locale\" content=\"ru_RU\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Design validation of recurrent signal processor FPGA prototype - \u041f\u0435\u0440\u0441\u043f\u0435\u043a\u0442\u0438\u0432\u043d\u044b\u0435 \u043f\u0443\u0442\u0438 \u0440\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 \u0430\u043f\u043f\u0430\u0440\u0430\u0442\u0443\u0440\u044b\" \/>\n<meta property=\"og:description\" content=\"Yury Stepchenkov, Dmitry Khilko, Yury Shikunov and Georgy Orlov. Design validation of recurrent signal processor FPGA prototype \/\/ Proceedings of IEEE East-West Design & Test Symposium (EWDTS\u20192021),  Batumi, Georgia, September, 10 — 13, 2021, P. 157-161. DOI: 10.1109\/EWDTS52692.2021.9581005. (Indexed in Scopus). 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Design validation of recurrent signal processor FPGA prototype \/\/ Proceedings of IEEE East-West Design & Test Symposium (EWDTS\u20192021),  Batumi, Georgia, September, 10 — 13, 2021, P. 157-161. DOI: 10.1109\/EWDTS52692.2021.9581005. (Indexed in Scopus). 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