https:\/\/rscf.ru\/en\/project\/25-19-00508\/<\/a><\/p>\n\n\n\nLibrary reference:<\/strong> Stepchenkov Yu. A., Diachenko Yu. G., Khilko D. V., Stepchenkov D. Yu., Diachenko D. Yu., Stepanov B. A. Self-timed shift register implementation according to synchronous counterpart Verilog-description. Highly Available Systems, 2025. V. 21. \u2116 3. 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\u043f\u0440\u043e\u0435\u043a\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f. \u0420\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0430\u043d\u044b \u0448\u0430\u0431\u043b\u043e\u043d\u044b \u0442\u0438\u043f\u043e\u0432\u044b\u0445 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 \u0441\u0434\u0432\u0438\u0433\u0430, \u0433\u0430\u0440\u0430\u043d\u0442\u0438\u0440\u0443\u044e\u0449\u0438\u0435 \u0430\u0434\u0435\u043a\u0432\u0430\u0442\u043d\u043e\u0435 \u043a\u043e\u043d\u0432\u0435\u0440\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u0435 \u043e\u043f\u0438\u0441\u0430\u043d\u0438\u044f \u0441\u0438\u043d\u0445\u0440\u043e\u043d\u043d\u043e\u0433\u043e \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430 \u0441\u0434\u0432\u0438\u0433\u0430 \u0432 \u0421\u0421-\u0440\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044e.<\/p>\n\n\n\n\u041f\u0440\u0430\u043a\u0442\u0438\u0447\u0435\u0441\u043a\u0430\u044f \u0437\u043d\u0430\u0447\u0438\u043c\u043e\u0441\u0442\u044c.<\/strong> \u0418\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u0435 \u043d\u0430 \u043f\u0440\u0430\u043a\u0442\u0438\u043a\u0435 \u043f\u0440\u0435\u0434\u043b\u043e\u0436\u0435\u043d\u043d\u043e\u0433\u043e \u043c\u0435\u0442\u043e\u0434\u0430 \u0438 \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0430\u043d\u043d\u044b\u0445 \u0448\u0430\u0431\u043b\u043e\u043d\u043e\u0432 \u0421\u0421-\u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 \u0441\u0434\u0432\u0438\u0433\u0430 \u0434\u043b\u044f \u0430\u0432\u0442\u043e\u043c\u0430\u0442\u0438\u0437\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u043e\u0433\u043e \u043b\u043e\u0433\u0438\u0447\u0435\u0441\u043a\u043e\u0433\u043e \u0441\u0438\u043d\u0442\u0435\u0437\u0430 \u0421\u0421-\u0441\u0445\u0435\u043c \u043f\u043e\u0437\u0432\u043e\u043b\u0438\u0442 \u043e\u0431\u043b\u0435\u0433\u0447\u0438\u0442\u044c \u0438 \u0443\u0441\u043a\u043e\u0440\u0438\u0442\u044c \u0438\u0445 \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u043a\u0443, \u0447\u0442\u043e \u043e\u0441\u043e\u0431\u0435\u043d\u043d\u043e \u0432\u0430\u0436\u043d\u043e \u0434\u043b\u044f \u043a\u0440\u0438\u0442\u0438\u0447\u0435\u0441\u043a\u0438\u0445 \u043e\u0431\u043b\u0430\u0441\u0442\u0435\u0439 \u043f\u0440\u0438\u043c\u0435\u043d\u0435\u043d\u0438\u044f \u043d\u0430 \u0441\u043e\u0432\u0440\u0435\u043c\u0435\u043d\u043d\u043e\u043c \u044d\u0442\u0430\u043f\u0435 \u0440\u0430\u0437\u0432\u0438\u0442\u0438\u044f \u0438 \u0432\u043d\u0435\u0434\u0440\u0435\u043d\u0438\u044f \u0446\u0438\u0444\u0440\u043e\u0432\u043e\u0439 \u0442\u0435\u0445\u043d\u043e\u043b\u043e\u0433\u0438\u0438.<\/p>\n\n\n\nAbstract:<\/strong> Current trends in the development and use of digital circuits that form the basis for computing and information-control systems implementation highlight the problem of their reliable operation under adverse conditions that are potential sources of soft errors and failures. Self-timed (ST) digital circuits, which serve as an alternative to synchronous counterparts, have a higher immunity to soft error sources due to hardware redundancy, two-phase operation, ST coding of the information signals, and mandatory control of the switching completion of all circuit cells in each phase. They operate stably in an extremely wide range of supply voltage and ambient temperature. The combination of ST circuit properties makes them a promising basis for reliable digital equipment implementation. However, despite the long history of their appearance and research, ST circuits have not yet found wide application. This is due, not least of all, to the difficulty of their manual design in comparison with synchronous counterparts and the lack of software that would help digital hardware designers solve this problem. This article is aimed at solving the formalization and automation problem of the ST circuit design and, in particular, typical representatives of sequential ST circuits, namely, shift registers. The article describes the development of a method and hardware and software tools providing efficient logical synthesis of ST shift registers based on their original synchronous Verilog description. This method is familiar to developers of synchronous digital equipment. It does not require high qualification in the field of ST circuits from designers. A concept for designing sequential type ST circuits is proposed, based on the initial Verilog description of a synchronous counterpart and providing an efficient result of automated logical synthesis with consumer characteristics close to the manual design result characteristics. Templates of typical shift registers are developed and represented, guaranteeing adequate conversion of a synchronous shift register description to its ST implementation, which has all the properties of ST circuits. The practical use of the proposed method and the developed shift register templates for automated logical synthesis of ST circuits will facilitate and speed up their development, which is especially important for critical areas of application at the current stage of development and implementation of digital technology, including robotic systems and computing complexes.<\/p>\n","protected":false},"excerpt":{"rendered":"\u0421\u0442\u0435\u043f\u0447\u0435\u043d\u043a\u043e\u0432 \u042e.\u0410., \u0414\u044c\u044f\u0447\u0435\u043d\u043a\u043e \u042e.\u0413., \u0425\u0438\u043b\u044c\u043a\u043e \u0414.\u0412., \u0421\u0442\u0435\u043f\u0447\u0435\u043d\u043a\u043e\u0432 \u0414.\u042e., \u0414\u044c\u044f\u0447\u0435\u043d\u043a\u043e \u0414.\u042e., \u0421\u0442\u0435\u043f\u0430\u043d\u043e\u0432 \u0411.\u0410. \u0420\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u0441\u0430\u043c\u043e\u0441\u0438\u043d\u0445\u0440\u043e\u043d\u043d\u044b\u0445 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 \u0441\u0434\u0432\u0438\u0433\u0430 \u043f\u043e Verilog-\u043e\u043f\u0438\u0441\u0430\u043d\u0438\u044e \u0441\u0438\u043d\u0445\u0440\u043e\u043d\u043d\u044b\u0445 \u0430\u043d\u0430\u043b\u043e\u0433\u043e\u0432 \/\/ \u0421\u0438\u0441\u0442\u0435\u043c\u044b \u0432\u044b\u0441\u043e\u043a\u043e\u0439 \u0434\u043e\u0441\u0442\u0443\u043f\u043d\u043e\u0441\u0442\u0438, 2025. \u0422. 21. \u2116 3. \u0421. 5\u221215. DOI: https:\/\/doi.org\/10.18127\/j20729472-202503-05. \u0418\u043d\u0434. \u0432 \u044f\u0434\u0440\u0435 \u0420\u0418\u041d\u0426, \u0412\u0410\u041a, \u0411\u0421 \u041a2. \u0424\u0438\u043d\u0430\u043d\u0441\u043e\u0432\u0430\u044f \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u0430: \u0418\u0441\u0441\u043b\u0435\u0434\u043e\u0432\u0430\u043d\u0438\u0435 \u0432\u044b\u043f\u043e\u043b\u043d\u0435\u043d\u043e \u0437\u0430 \u0441\u0447\u0435\u0442 \u0433\u0440\u0430\u043d\u0442\u0430 \u0420\u043e\u0441\u0441\u0438\u0439\u0441\u043a\u043e\u0433\u043e \u043d\u0430\u0443\u0447\u043d\u043e\u0433\u043e \u0444\u043e\u043d\u0434\u0430 \u2116 25-19-00508, https:\/\/rscf.ru\/project\/25-19-00508\/ \/ FundingAgency: […]<\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[65,55,54,1,12,62,52,53,59],"tags":[],"class_list":["post-3577","post","type-post","status-publish","format-standard","hentry","category-65","category-dyachenko-d-yu","category-dyachenko-yu-g","category-publications","category-samosinhronnaya-shemotehnika","category-stepanov-b-a","category-stepchenkov-d-yu","category-stepchenkov-yu-a","category-hilko-d-v"],"yoast_head":"\n
\u0420\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u0441\u0430\u043c\u043e\u0441\u0438\u043d\u0445\u0440\u043e\u043d\u043d\u044b\u0445 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 \u0441\u0434\u0432\u0438\u0433\u0430 \u043f\u043e Verilog-\u043e\u043f\u0438\u0441\u0430\u043d\u0438\u044e \u0441\u0438\u043d\u0445\u0440\u043e\u043d\u043d\u044b\u0445 \u0430\u043d\u0430\u043b\u043e\u0433\u043e\u0432 - \u041f\u0435\u0440\u0441\u043f\u0435\u043a\u0442\u0438\u0432\u043d\u044b\u0435 \u043f\u0443\u0442\u0438 \u0440\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 \u0430\u043f\u043f\u0430\u0440\u0430\u0442\u0443\u0440\u044b<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"http:\/\/selftiming.ru\/new\/2025\/10\/16\/realizacziya-samosinhronnyh-registrov-sdviga-po-verilog-opisaniyu-sinhronnyh-analogov\/\" \/>\n<meta property=\"og:locale\" content=\"ru_RU\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"\u0420\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u0441\u0430\u043c\u043e\u0441\u0438\u043d\u0445\u0440\u043e\u043d\u043d\u044b\u0445 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 \u0441\u0434\u0432\u0438\u0433\u0430 \u043f\u043e Verilog-\u043e\u043f\u0438\u0441\u0430\u043d\u0438\u044e \u0441\u0438\u043d\u0445\u0440\u043e\u043d\u043d\u044b\u0445 \u0430\u043d\u0430\u043b\u043e\u0433\u043e\u0432 - \u041f\u0435\u0440\u0441\u043f\u0435\u043a\u0442\u0438\u0432\u043d\u044b\u0435 \u043f\u0443\u0442\u0438 \u0440\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 \u0430\u043f\u043f\u0430\u0440\u0430\u0442\u0443\u0440\u044b\" \/>\n<meta property=\"og:description\" content=\"\u0421\u0442\u0435\u043f\u0447\u0435\u043d\u043a\u043e\u0432 \u042e.\u0410., \u0414\u044c\u044f\u0447\u0435\u043d\u043a\u043e \u042e.\u0413., \u0425\u0438\u043b\u044c\u043a\u043e \u0414.\u0412., \u0421\u0442\u0435\u043f\u0447\u0435\u043d\u043a\u043e\u0432 \u0414.\u042e., \u0414\u044c\u044f\u0447\u0435\u043d\u043a\u043e \u0414.\u042e., \u0421\u0442\u0435\u043f\u0430\u043d\u043e\u0432 \u0411.\u0410. \u0420\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u0441\u0430\u043c\u043e\u0441\u0438\u043d\u0445\u0440\u043e\u043d\u043d\u044b\u0445 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 \u0441\u0434\u0432\u0438\u0433\u0430 \u043f\u043e Verilog-\u043e\u043f\u0438\u0441\u0430\u043d\u0438\u044e \u0441\u0438\u043d\u0445\u0440\u043e\u043d\u043d\u044b\u0445 \u0430\u043d\u0430\u043b\u043e\u0433\u043e\u0432 \/\/ \u0421\u0438\u0441\u0442\u0435\u043c\u044b \u0432\u044b\u0441\u043e\u043a\u043e\u0439 \u0434\u043e\u0441\u0442\u0443\u043f\u043d\u043e\u0441\u0442\u0438, 2025. \u0422. 21. \u2116 3. \u0421. 5\u221215. DOI: https:\/\/doi.org\/10.18127\/j20729472-202503-05. \u0418\u043d\u0434. \u0432 \u044f\u0434\u0440\u0435 \u0420\u0418\u041d\u0426, \u0412\u0410\u041a, \u0411\u0421 \u041a2. \u0424\u0438\u043d\u0430\u043d\u0441\u043e\u0432\u0430\u044f \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u0430: \u0418\u0441\u0441\u043b\u0435\u0434\u043e\u0432\u0430\u043d\u0438\u0435 \u0432\u044b\u043f\u043e\u043b\u043d\u0435\u043d\u043e \u0437\u0430 \u0441\u0447\u0435\u0442 \u0433\u0440\u0430\u043d\u0442\u0430 \u0420\u043e\u0441\u0441\u0438\u0439\u0441\u043a\u043e\u0433\u043e \u043d\u0430\u0443\u0447\u043d\u043e\u0433\u043e \u0444\u043e\u043d\u0434\u0430 \u2116 25-19-00508, https:\/\/rscf.ru\/project\/25-19-00508\/ \/ FundingAgency: […]\" \/>\n<meta property=\"og:url\" content=\"http:\/\/selftiming.ru\/new\/2025\/10\/16\/realizacziya-samosinhronnyh-registrov-sdviga-po-verilog-opisaniyu-sinhronnyh-analogov\/\" \/>\n<meta property=\"og:site_name\" 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