{"id":645,"date":"2017-12-24T12:38:00","date_gmt":"2017-12-24T09:38:00","guid":{"rendered":"http:\/\/selftiming.ru\/new\/?p=645"},"modified":"2023-04-07T13:48:51","modified_gmt":"2023-04-07T10:48:51","slug":"self-timed-floating-point-multiply-add-unit","status":"publish","type":"post","link":"http:\/\/selftiming.ru\/new\/2017\/12\/24\/self-timed-floating-point-multiply-add-unit\/","title":{"rendered":"Self-Timed Floating Point Multiply-Add Unit"},"content":{"rendered":"\n

Y.A. Stepchenkov, Y.V. Rogdestvenski, Y.G. Diachenko, N.V. Morozov, D.Y. Stepchenkov, B.A. Stepanov, D.Y. Diachenko, A.V. Rogdestvenskene. Self-Timed Floating Point Multiply-Add Unit \/\/ Problems of Advanced Micro- and Nanoelectronic Systems Development, 2017, Part III, Moscow, IPPM RAS, P. 45-51. <\/strong>(is indexed in Scopus).<\/p>\n\n\n\n

Abstract:<\/strong> The subject of this paper is a Speed-Independent Floating  Point  Coprocessor  (SIFPC)  implementing  Fused Multiply-Add-Subtract  operation.  It  utilizes  mixed  dual-rail and  redundant  self-timed  coding,  and  is   compliant  with IEEE  754  Standard.  SIFPC  processes  either  one  operation with  double  precision  numbers,  or  two  simultaneous  opera-tions  with  single  precision  numbers,  and  calculates  two  re-sults: sum  and  difference between  product  of first two oper-ands  and  third  operand.  SIFPC  consists  of  two  identical channels  with  common  input  and  output.  An  order  of  data outputting matches the order of an input data. Each channel implements  full  data  processing  path  and  has  two  pipeline stages:  first  is  multiplier  and  exponent  calculation,  and  se-cond is all rest parts. This reduces hardware complexity and accelerates  calculations  due  to  reducing  number  of  interme-diate  registers  and  cutting  number  of  «bottlenecks»  in  an indication  subcircuit  of  the  unit.  An  additional  speed-up  of performance,  comparing  to  a  traditional  self-timed  circuit implementation,  is  achieved  due  to  utilizing  bit-wise  and simplified  (adaptive)  indication.  Multiplier  utilizes  modified Booth  algorithm  with  Wallace  tree,  self-timed  redundant code  and  ternary  adders.  First  stage  of  the  Wallace  tree compresses  four  dual-rail  partial  products  into  two  ternary operands.  The  unit  is  designed  for  standard  65-nm  CMOS process.  It  has  1.12  mm2  die  size,  demonstrates  3.15  Gflops performance and 1.8 ns latency.<\/p>\n\n\n\n

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Y.A. Stepchenkov, Y.V. Rogdestvenski, Y.G. Diachenko, N.V. Morozov, D.Y. Stepchenkov, B.A. Stepanov, D.Y. Diachenko, A.V. Rogdestvenskene. Self-Timed Floating Point Multiply-Add Unit \/\/ Problems of Advanced Micro- and Nanoelectronic Systems Development, 2017, Part III, Moscow, IPPM RAS, P. 45-51. (is indexed in Scopus). Abstract: The subject of this paper is a Speed-Independent Floating  Point  Coprocessor  (SIFPC)  […]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[32,55,54,51,56,57,12,62,52,53,4],"tags":[],"class_list":["post-645","post","type-post","status-publish","format-standard","hentry","category-32","category-dyachenko-d-yu","category-dyachenko-yu-g","category-morozov-n-v","category-rozhdestvenskene-a-v","category-rozhdestvenskij-yu-v","category-samosinhronnaya-shemotehnika","category-stepanov-b-a","category-stepchenkov-d-yu","category-stepchenkov-yu-a","category-conferences"],"yoast_head":"\nSelf-Timed Floating Point Multiply-Add Unit - \u041f\u0435\u0440\u0441\u043f\u0435\u043a\u0442\u0438\u0432\u043d\u044b\u0435 \u043f\u0443\u0442\u0438 \u0440\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 \u0430\u043f\u043f\u0430\u0440\u0430\u0442\u0443\u0440\u044b<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"http:\/\/selftiming.ru\/new\/2017\/12\/24\/self-timed-floating-point-multiply-add-unit\/\" \/>\n<meta property=\"og:locale\" content=\"ru_RU\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Self-Timed Floating Point Multiply-Add Unit - \u041f\u0435\u0440\u0441\u043f\u0435\u043a\u0442\u0438\u0432\u043d\u044b\u0435 \u043f\u0443\u0442\u0438 \u0440\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 \u0430\u043f\u043f\u0430\u0440\u0430\u0442\u0443\u0440\u044b\" \/>\n<meta property=\"og:description\" content=\"Y.A. Stepchenkov, Y.V. Rogdestvenski, Y.G. Diachenko, N.V. Morozov, D.Y. Stepchenkov, B.A. Stepanov, D.Y. Diachenko, A.V. Rogdestvenskene. Self-Timed Floating Point Multiply-Add Unit \/\/ Problems of Advanced Micro- and Nanoelectronic Systems Development, 2017, Part III, Moscow, IPPM RAS, P. 45-51. (is indexed in Scopus). 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Stepchenkov, Y.V. Rogdestvenski, Y.G. Diachenko, N.V. Morozov, D.Y. Stepchenkov, B.A. Stepanov, D.Y. Diachenko, A.V. Rogdestvenskene. Self-Timed Floating Point Multiply-Add Unit \/\/ Problems of Advanced Micro- and Nanoelectronic Systems Development, 2017, Part III, Moscow, IPPM RAS, P. 45-51. (is indexed in Scopus). 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