Iterator component development for data redundancy solution in data-flow architecture

Yury A. Stepchenkov, Dmitry V. Khilko, Yury I. Shikunov, Georgii A. Orlov.  Iterator component development for data redundancy solution in data-flow architecture // 2020 IEEE Conference of Russian Young Researchers…

Self-Timed Multiply-add-subtract Unit Alternates

Yury A. Stepchenkov, Yury G. Diachenko, Yury V. Rogdestvenski, Denis Y. Diachenko, Yury I. Shikunov.  Self-Timed Multiply-add-subtract Unit Alternates // 2020 IEEE Conference of Russian Young Researchers in Electrical and…