Специализированные преобразователи тегов для рекуррентного обработчика сигналов

Степченков Ю.А., Хилько Д.В., Шикунов Ю.И., Орлов Г.А. Специализированные преобразователи тегов для рекуррентного обработчика сигналов // Проблемы разработки перспективных микро- и наноэлектронных систем — 2020. Сборник трудов под общ. ред. академика РАН А.Л. Стемпковского, М.: ИППМ РАН, 2020. Выпуск 2. С. 73-80.
DOI: 10.31114/2078-7707-2020-2-73-80

Аннотация: Настоящая статья посвящена исследованию применимости специализированных рекуррентных преобразователей в рекуррентном операционном устройстве для задач цифровой обработки сигналов. Рассматриваются основные особенности и существующие проблемы реализации рекуррентности в операционном устройстве, построенном на основе потокового (data-flow) принципа. Приводится анализ ограниченного подмножества алгоритмов цифровой обработки сигналов с целью построения специализированных рекуррентных цепочек и преобразователей их реализующих. Представлены результаты построения некоторых специализированных преобразователей тегов и реализации демонстрационного алгоритма фильтрации Баттерворта.

Testing and optimization of Recurrent Signal Processor

Yury Stepchenkov, Dmitry Khilko, Yury Shikunov, Georgy Orlov. Testing and optimization of Recurrent Signal Processor // 2020 International Conference Engineering Technologies and Computer Science EnT 2020 Moscow, Russia24-27 June 2020. P. 54-57. (indexed in Scopus).
DOI: 10.1109/EnT48576.2020.00017

Abstract: This paper covers the optimization research for the novel data-flow computational architecture called Hybrid Architecture of Recurrent Signal Processor. The testing methodology, based on the shift towards Test-Driven Development of architecture models, is provided. We cover the toolset developed to unify the methodology for both software and hardware models. The testing results are analyzed, and the issues are formulated. We propose the pipeline extension by splitting our largest component down. We show the new pipeline utilization ratio this solution provides.

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Iterator component development for data redundancy solution in data-flow architecture

Yury A. Stepchenkov, Dmitry V. Khilko, Yury I. Shikunov, Georgii A. Orlov.  Iterator component development for data redundancy solution in data-flow architecture // 2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus) Moscow, Russia, January 27-30, 2020. — IEEE, P. 1869-1872. (indexed in Scopus).
DOI: 10.1109/EIConRus49466.2020.9039358

Abstract: The hardware sample of multi-core data-flow recurrent architecture has been developed and tested on the digital signal processing domain. An analysis of the iterative algorithms execution results made it possible to propose a number of mechanisms to improve one of the components of the architecture — the Iterator. A significant problem in architecture programming is a high program redundancy produced by a significant number of special operands that are designed to control its internal resources. The Iterator component is designed to solve this issue, but its capabilities were not enough. The article presents the development results of the Iterator component. A description of the developed mechanisms to control the Iterator is provided. We demonstrate the results of the Iterator improvements using an example of the Viterbi algorithm for searching at hidden Markov models. The developed tools made it possible to nearly halve the volume of special operands and optimize the software implementation of the algorithm

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Development of Capsule Programming Means for Recurrent Data-flow Architecture

D.V. Khilko, Yu. A. Stepchenkov, Yu.I. Shikunov, G.A. Orlov. Development of Capsule Programming Means for Recurrent Data-flow Architecture // Problems of Advanced Micro- and Nanoelektronic Systems Development – 2019, Issue II, Moscow, IPPM RAS, P. 40-45.
DOI: 10.31114/2078-7707-2019-2-40-45

Abstract: This paper presents new results obtained in the course of work on the development of methods and tools for software programming and debugging of the multicore re-current data-flow architecture (MRDA). At the current stage of development, the main goal is to automate the construc-tion of a special programmer’s tool – graph-capsules (GC), which visualizes the distribution of computing resources of the MRDA. To automate its creation, a component was de-veloped to construct GC in numerical form, using the model-ling results. The next step in the development of program-ming toolset is the creation of tools for graph and GC con-struction based on their symbolic form, which lays the foun-dation for the creation of the compilation tools in the future. This paper is dedicated to discussing the results of solving this problem.

Modeling and debugging tools development for recurrent architecture

Dmitry Khilko, Yuri Stepchenkov, Yury Shikunov and George Orlov. Modeling and debugging tools development for recurrent architecture  // 2019 IEEE EAST-WEST DESIGN & TEST SYMPOSIUM Batumi, Georgia, September 13 — 16, 2019.
DOI: 10.1109/EWDTS.2019.8884412

Abstract: An unconventional multi-core recurrent data-flow architecture, that is being developed at Federal Research Center “Computer Science and Control” of the Russian Academy of Sciences (FRS CSC RAS)was successfully tested on digital signal processing domain both at the model level and on a hardware sample. Based on the test results, several mechanisms had been identified that required improvement and a decision was made to investigate the architecture on other subject domains. Software and main architectural blocks debugging are carried out with the specially developed hardware and software modeling tools. The active extension and debugging of the architecture by using these tools revealed a number of shortcomings of the existing software. To eliminate these shortcomings, two problems have to be solved: to provide a high degree of reconfigurability of the architecture’s imitational model (to debug its mechanisms)and implement a symbolic modeling mode (to debug its software). The redesigning results of modeling and debugging tools for recurrent data-flow architecture are discussed in the article.

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Hybrid multi-core recurrent architecture approbation on FPGA

Yury Stepchenkov, Nikolai Morozov, Dmitry Khilko, Yury Shikunov, Georgy Orlov. Hybrid multi-core recurrent architecture approbation on FPGA // 2019 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus) January 28-31, 2019, Moscow, Russia. (indexed in Scopus).
DOI: 10.1109/EIConRus.2019.8657140

Abstract: This paper provides approbation results of the multi-core hybrid architecture for recurrent signal processing (HARSP) as a hardware sample. The prototype has been designed primarily to check architecture’s integrity and universality on digital signal processing domain and to verify the hardware implementation of its imitational model, while operational frequency has not been as relevant. Hardware sample has been implemented on FPGA basis with Cyclone V GT Development Kit. Every data-flow processor implements fixed-point 16-bit processing core while the control level is implemented via generated NIOS II processor. The isolated word recognition with a high confidence threshold (at least 95% with a noise level of 15 dB) has been selected as the subject area. We compare HARSP efficiency against specialized TI C66x DSP by implementing the subset of BTDImark2000 algorithms, using computational steps amount the comparison metric.

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Развитие средств капсульного программирования потоковой рекуррентной архитектуры

Д.В. Хилько, Ю.А. Степченков, Ю.И. Шикунов, Г.А. Орлов. Развитие средств капсульного программирования потоковой рекуррентной архитектуры // Проблемы разработки перспективных микро- и наноэлектронных систем – 2018. Сборник трудов под общ. ред. академика РАН А.Л. Стемпковского, М.: ИППМ РАН, 2018. Часть III. С. 2–9.
DOI: 10.31114/2078-7707-2018-3-2-9

Аннотация: В статье рассматриваются новые результаты, полученные в ходе работ по направлению разработки методов и средств программирования многоядерной потоковой рекуррентной архитектуры. На текущем этапе разработки основной целью является автоматизация построения специального инструмента программиста – графкапсулы, который позволяет наглядно отображать распределение ресурсов архитектуры в процессе выполнения программы. Для этого был разработан компонент построения граф-капсул в числовом виде, использующий результаты моделирования. Следующим шагом в развитии средств программирования является разработка инструментария для построения потоковых графов и граф-капсул на их основе в символьном виде, что позволит заложить основу для создания средств компиляции в будущем. Обсуждению результатов решения данной задачи посвящена настоящая статья.

Graph-capsule construction toolset for data-flow computer architecture

Yu. Shikunov, Yu. Stepchenkov, D. Khilko, G. Orlov. Graph-capsule construction toolset for data-flow computer architecture // 2018 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus) 29 Jan.-1 Feb., 2018, Moscow, Russia. (indexed in Scopus).

Abstract: This paper covers the technical aspects of developing elements of methodology and software for multicore recurrent data-flow architecture. Nowadays capsule programming is similar to assembler: high efficiency accompanied by high complexity and unintuitiveness. We develop specialized toolset suite for creating and debugging software for hybrid architecture for recurrent signal processing called HARSP IDE. One of the toolsets included is the specialized data-flow graph builder that constructs graph-capsules. Automatic graph-capsule construction significantly reduces development complexity by providing visual overview of computational process and resource utilization. The paper covers development stages, architecture and functionality of graph builder. We show case the tool on Viterbi algorithm debugging.

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Recurrent mechanism developments in the data-flow computer architecture

Yu. Shikunov, Yu. Stepchenkov, D. Khilko. Recurrent mechanism developments in the data-flow computer architecture // 2018 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus) 29 Jan.-1 Feb., 2018, Moscow, Russia. (indexed in Scopus). P. 1413 – 1418
DOI: 10.1109/EIConRus.2018.8317362

Abstract: This paper covers non-conventional recurrent data-flow architecture, its features, and implementation aspects. Recurrence — the main feature of the new architecture efficiently solves data redundancy problem, typical for data-flow architectures while increasing performance. Conventional recurrence implementation has an overhead of configuration operand insertion that provides required functional fields (tags). Functional capabilities expansion of the architecture mechanism implementing this feature resulted in further efficiency by eliminating said overhead in some instances. We cover enhancements implemented in multicore recurrent data-flow architecture, designed to increase the versatility of recurrent computational process utilization. We compare Viterbi algorithm implementations with and without enhancements.

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Recurrent data-flow architecture: technical aspects of implementation and modeling results

D.V. Khilko, Yu. A. Stepchenkov, D. I. Shikunov, Yu. I. Shikunov. Recurrent data-flow architecture: technical aspects of implementation and modeling results // Problems of Advanced Micro- and Nanoelectronic Systems Development, 2017, Part II, Moscow, IPPM RAS, P. 59-64.

Abstract: The paper covers methods and features of implementing a prototype architecture based on a new recurrent data-flow paradigm of computing designed to solve problems of digital signal processing. Demonstration of key principles and technical solutions implemented in the new architecture is presented, with the example of the Fast Fourier Transform task, as well as estimation of the speed of this task with respect to its solutions on processors of traditional single-core and specialized data-flow multi-core architectures. Comparative estimates of the effectiveness of the implementation of algorithms for isolated words recognition in the environment of the recurrent architecture with respect to von Neumann single-core one are shown.