Iterator component development for data redundancy solution in data-flow architecture

Yury A. Stepchenkov, Dmitry V. Khilko, Yury I. Shikunov, Georgii A. Orlov.  Iterator component development for data redundancy solution in data-flow architecture // 2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus) Moscow, Russia, January 27-30, 2020. — IEEE, P. 1869-1872. (indexed in Scopus).
DOI: 10.1109/EIConRus49466.2020.9039358

Abstract: The hardware sample of multi-core data-flow recurrent architecture has been developed and tested on the digital signal processing domain. An analysis of the iterative algorithms execution results made it possible to propose a number of mechanisms to improve one of the components of the architecture — the Iterator. A significant problem in architecture programming is a high program redundancy produced by a significant number of special operands that are designed to control its internal resources. The Iterator component is designed to solve this issue, but its capabilities were not enough. The article presents the development results of the Iterator component. A description of the developed mechanisms to control the Iterator is provided. We demonstrate the results of the Iterator improvements using an example of the Viterbi algorithm for searching at hidden Markov models. The developed tools made it possible to nearly halve the volume of special operands and optimize the software implementation of the algorithm

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