Zatsarinny A.A., Stepchenkov Yu. A., Diachenko Yu. G., Rogdestvenski Yu. V., Plekhanov L.P. Failure-tolerant self-timed circuits // Russian Microelectronics, 2023. Vol. 52. No. 8. P. 793-797. © Pleiades Publishing, Ltd., 2023.
DOI: 10.1134/S1063739723080061. Indexed in Scopus, ВАК, Ринц, БС2. EDN: ZBDTDQ.
Финансовая поддержка: Исследование выполнено в рамках государственного задания № 0063-2019-0010. / Funding Agency: The study was carried out within the framework of state assignment No. 0063-2019-0010.
Abstract: The article considers the problem of developing synchronous and self-timed (ST) circuits that are tolerant to failures. Redundant ST coding and two-phase discipline ensures that ST circuits are more tolerant to soft errors than synchronous counterparts. Duplicating ST channels instead of tripling reduces the failure-tolerant ST circuit’s hardware redundancy and retains its reliability in higher level compared to synchronous counterparts.