Stepchenkov Yu.A., Morozov N.V., Diachenko Yu.G., Khilko D.V., Stepchenkov D.Yu., Shikunov Yu.I. Hardware implementation of the digital signal processing algorithms in recurrent signal processor on FPGA // Russian Microeleсtronics, 2023, Vol. 52. Iss. 7. P. 630–632.
Doi: 10.1134/S106373972307017X. Indexed in Scopus, ВАК, Ринц.
Финансовая поддержка: Исследование выполнено в рамках государственного задания № 0063-2019-0010. / Funding Agency: The study was carried out within the framework of state assignment No. 0063-2019-0010.
Abstract: Dataflow architecture is an alternative to traditional von Neumann computing architecture. However, known variants of dataflow architecture have a range of serious problems with no effective solutions up to the present day. This paper represents Hybrid Recurrent Signal Processor’s (HRSP) hardware verification results. It describes HRSP’s register transfer level model implementing its architectural specification and hardware prototype on the HAN Pilot Platform development board with Intel Arria10 field-programmable gate array. HRSP consists of a von Neumann master processor on a control layer and a recurrent dataflow unit on an operational layer. Dataflow unit includes four computing cores. HRSP’s hardware model combines either software or hardware implementation of the control processor and the hardware model of the operational layer. Testing the HRSP’s hardware prototype on the development board using an isolated word recognizer (IWR) as a typical data processing application has proven that the hardware model is bit-exact with both HRSP’s imitation model and the original IWR C++ model. The HRSP’s hardware prototype’s achieved performance ensures IWR’s operation in real-time mode on the development board. It is slightly better than the performance of the TMSC55x (Texas Instruments) digital signal processor. Verification of the HRSP’s hardware implementation on synthetic tests showed that its average performance is 5% higher than the performance of the DSP TMSC55x digital signal processor. The results of the proposed optimization of hardware support for Fast Fourier Transform (FFT) in HRSP prove that such an optimization speeds up the FFT calculation, significantly reduces the capsule size, reduces the required hardware resources and simplifies FFT scaling.