Hybrid multi-core recurrent architecture approbation on FPGA

Yury Stepchenkov, Nikolai Morozov, Dmitry Khilko, Yury Shikunov, Georgy Orlov. Hybrid multi-core recurrent architecture approbation on FPGA // 2019 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus) January 28-31, 2019, Moscow, Russia. (indexed in Scopus).
DOI: 10.1109/EIConRus.2019.8657140

Abstract: This paper provides approbation results of the multi-core hybrid architecture for recurrent signal processing (HARSP) as a hardware sample. The prototype has been designed primarily to check architecture’s integrity and universality on digital signal processing domain and to verify the hardware implementation of its imitational model, while operational frequency has not been as relevant. Hardware sample has been implemented on FPGA basis with Cyclone V GT Development Kit. Every data-flow processor implements fixed-point 16-bit processing core while the control level is implemented via generated NIOS II processor. The isolated word recognition with a high confidence threshold (at least 95% with a noise level of 15 dB) has been selected as the subject area. We compare HARSP efficiency against specialized TI C66x DSP by implementing the subset of BTDImark2000 algorithms, using computational steps amount the comparison metric.

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