Speed-Independent Floating Point Coprocessor

Stepchenkov Yuri, Zakharov Victor, Rogdestvenski Yuri, Diachenko Yuri, Morozov Nickolaj and Stepchenkov Dmitri. Speed-Independent Floating Point Coprocessor // Proceedings of IEEE East-West Design & Test Symposium (EWDTS’2015), Batumi, Georgia, September 26 — 29, 2015. P. 111-114.

Speed-independent fused multiply-add unit as a coprocessor is represented. It purely conforms to IEEE 754 Standard. For minimization hardware and power consumption, a number of pipeline stages is reduced down to two. Wallace tree in the multiplier utilizes redundant self-timed code. Represented unit is developed on a base of standard 65-nm CMOS bulk process. It provides a performance up to 0.54 Gflops, and power consumption at level of 450 mW/Gflops

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