Recurrent mechanism developments in the data-flow computer architecture

Yu. Shikunov, Yu. Stepchenkov, D. Khilko. Recurrent mechanism developments in the data-flow computer architecture //2018 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus) Moscow, Russia, 29 Jan.-1 Feb., 2018. —IEEE, P. 1413 – 1418. (indexed in Scopus).
DOI: 10.1109/EIConRus.2018.8317362

Abstract: This paper covers non-conventional recurrent data-flow architecture, its features, and implementation aspects. Recurrence — the main feature of the new architecture efficiently solves data redundancy problem, typical for data-flow architectures while increasing performance. Conventional recurrence implementation has an overhead of configuration operand insertion that provides required functional fields (tags). Functional capabilities expansion of the architecture mechanism implementing this feature resulted in further efficiency by eliminating said overhead in some instances. We cover enhancements implemented in multicore recurrent data-flow architecture, designed to increase the versatility of recurrent computational process utilization. We compare Viterbi algorithm implementations with and without enhancements.

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