I.A. Sokolov, Y.V. Rogdestvenski, Y.G. Diachenko, Y.A. Stepchenkov, N.V. Morozov, D.Y. Stepchenkov, D.Y. Diachenko. Delay-Insensitive Floating Point Multiply-Add-Subtract Unit / Problems of Advanced Micro- and Nanoelektronic Systems Development – 2019, Issue III, Moscow, IPPM RAS, P. 20-25. (is indexed in Scopus).
The subject of this paper is a floating point unit implementing fused multiply-add-subtract operation. It be-longs to the delay-insensitive self-timed (ST) circuits which do not depend on delays both in cells and on wires. It is fully compliant with IEEE 754 Standard and processes both a sum and difference between product of first two operands and third operand. Each 64-bit input operand contains either one double precision number, or two single precision numbers. Thus presented unit calculates either one operation with double precision numbers, or two simultaneous operations with single precision numbers. Multiplier utilizes modified Booth algorithm. In order to increase its performance, it is divided into two pipeline stages with accelerated forced switching to spacer phase. Booth encoder circuit is integrated into an input FIFO. FIFO is implemented as a register file with an output multiplexer and read/write address counters. Using ternary redundant ST code for multiplying, adding and subtracting provides reduction of unit’s complexity. Indication subcircuit considers the constrains imposed by an isochronous area for chosen fabrication technology. For de-creasing energy consumption, the fused multiply-add-subtract unit implements one-channel pipeline. The unit is designed for 65-nm CMOS bulk technology using an indus-trial standard cell library supplemented by self-timed cells. It provides 3 Gflops performance and 2.9-ns latency