Speed-Independent Fused Multiply Add and Subtract Unit

Yuri Stepchenkov, Victor Zakharov, Yuri Rogdestvenski, Yuri Diachenko, Nikolai Morozov and Dmitri Stepchenkov. Speed-Independent Fused Multiply Add and Subtract Unit // Proceedings of IEEE East-West Design & Test Symposium (EWDTS’2016), Yerevan, October, 14 — 17, 2016. P. 150-153. (is indexed in Scopus).


Speed -independent fused multiply-add -subtract unit is offered together with test environment providing full verification of its performance and workability in all range of the environment conditions. It complies with IEEE 754 Standard, and performs double and single precision operations at three operands. The unit is implemented as a two-channel with a common input and output . Each channel is a pipeline with four stag-es. Multiplier is implemented on the modified Booth algorithm using self -timed redundant code. The unit was design ed on a base of standard CMOS processwith 65 nm design rules and has 3.15 Gigaflops per-formance and less than 2 ns latency

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