A.A. Zatsarinny, Yu. A. Stepchenkov, Yu. G. Diachenko, Yu. V. Rogdestvenski. Failure-tolerant synchronous and self-timed circuits comparison. // Russian Microelectronics, 2022, Vol. 51, No. 8, P. 630–632. © Pleiades Publishing, Ltd., 2022. Published: 19 March 2023.
DOI: 10.1134/S1063739722080091. Indexed in Scopus, ВАК, Ринц. URL: https://link.springer.com/article/10.1134/S1063739722080091.
Финансовая поддержка: Исследование выполнено в рамках государственного задания № 0063-2019-0010. / Funding Agency: The study was carried out within the framework of state assignment No. 0063-2019-0010.
Abstract: The article considers the problem of developing synchronous and self-timed (ST) digital circuits tolerant to soft errors. Synchronous circuits traditionally use the “2-of-3” voting principle to ensure a single failure, resulting in three times the hardware costs. Due to dual-rail signal coding and two-phase control in ST circuits, duplication provides a soft error tolerance level 2.1 to 3.5 times higher than the triple modular redundant synchronous counterpart. The development of new high-precision software simulating microelectronic failure mechanisms will provide more accurate estimates for the electronic circuits’ failure tolerance.