Dmitry Khilko, Yuri Stepchenkov, Yury Shikunov and George Orlov. Modeling and debugging tools development for recurrent architecture // 2019 IEEE EAST-WEST DESIGN & TEST SYMPOSIUM Batumi, Georgia, September 13 — 16, 2019.
Abstract: An unconventional multi-core recurrent data-flow architecture, that is being developed at Federal Research Center “Computer Science and Control” of the Russian Academy of Sciences (FRS CSC RAS)was successfully tested on digital signal processing domain both at the model level and on a hardware sample. Based on the test results, several mechanisms had been identified that required improvement and a decision was made to investigate the architecture on other subject domains. Software and main architectural blocks debugging are carried out with the specially developed hardware and software modeling tools. The active extension and debugging of the architecture by using these tools revealed a number of shortcomings of the existing software. To eliminate these shortcomings, two problems have to be solved: to provide a high degree of reconfigurability of the architecture’s imitational model (to debug its mechanisms)and implement a symbolic modeling mode (to debug its software). The redesigning results of modeling and debugging tools for recurrent data-flow architecture are discussed in the article.
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